Intel Xeon 6 & AMD EPYC 9005 —
Complete buyer guide & specification reference

Intel's Xeon 6 ships in two distinct variants. P-cores (Performance cores) are full-featured cores with Hyper-Threading, large caches, and higher IPC — best for latency-sensitive, single-threaded-heavy workloads like EDA and databases. E-cores (Efficiency cores) are smaller, power-efficient cores optimised for throughput — they sacrifice per-core performance to pack more cores per watt, ideal for web serving, containers, and scale-out compute. P-cores and E-cores use different sockets and chipsets — they are not interchangeable on the same motherboard.

In a 2-socket (2P) server, each CPU has its own memory channels. Memory connected to CPU 0 is "local" to CPU 0 and "remote" to CPU 1 — and accessing remote memory adds ~40–80ns extra latency. This is NUMA. NUMA-aware applications (databases, VMware, HPC solvers) pin workloads to a single socket and its local memory to avoid this penalty. Poorly configured VMs that straddle NUMA domains can see 20–30% performance degradation.

The number of independent memory buses between the CPU and DRAM. More channels = more parallel bandwidth. AMD EPYC 9005 leads with 12 channels (vs Intel Xeon 6 E-core's 8 channels). Populating all channels symmetrically is critical — leaving channels empty reduces aggregate bandwidth. A 2P EPYC 9005 server with all 24 channels populated runs at ~700 GB/s aggregate memory bandwidth.

PCIe lanes connect the CPU directly to GPUs, NVMe SSDs, and high-speed NICs. An 8× GPU server needs 8× PCIe x16 slots = 128 lanes, all from a single CPU. Both AMD EPYC 9005 and Intel Xeon 6 P-core provide 128–136 lanes — enough for 8-GPU configurations without needing PLX switches (which add latency). PCIe 5.0 doubles bandwidth over PCIe 4.0 per lane.

Modern server CPUs include dedicated matrix computation hardware for AI inference without a GPU. Intel AMX (Advanced Matrix Extensions) accelerates BF16 and INT8 matrix operations directly in silicon. AMD Zen 5 doubles the AVX-512 execution width and includes VNNI instructions for INT8 neural network operations. These allow cost-effective AI inference on CPU-only nodes for smaller models (BERT, ResNet, text classification) where GPU provisioning isn't justified.

AMD EPYC 9005 uses a chiplet design — multiple Compute Complex Dies (CCDs) built on TSMC 3nm, connected to a central I/O Die (IOD) on TSMC 6nm. Each CCD contains 24 Zen 5 cores and 48MB L3 cache. The EPYC 9965 has 8 CCDs = 192 cores. Intel Xeon 6 uses a different tiled architecture. Chiplet designs allow AMD to build extremely high core-count CPUs cost-effectively.