A peer-reviewed roadmap from SK hynix and five universities has put hard numbers on co-packaged optics: 100Tb/s per node, under 1pJ per bit, sub-10ns latency. For UK buyers planning AI cluster refreshes, these targets need to shape RFP language now, not after the next fabric is already ordered.
View the data behind this chart
| Spectrum-X Photonics | SN6800 | |
|---|---|---|
| Total Switch Bandwidth | Tb/s102.4 | Tb/s409.6 |
Why the AI Cluster Bottleneck Moved to the Fabric
High Bandwidth Memory solved the problem of feeding data to an individual accelerator package. It did not solve the much bigger problem of moving data between tens of thousands of accelerators spread across racks and pods. According to the Nature Electronics perspective paper published on 20 August and co-authored by SK hynix, the University of Virginia, UIUC, MIT, Nanyang Technological University and Yonsei University, compute throughput in distributed AI clusters has grown roughly 3x every two years, while interconnect bandwidth has managed only about 1.4x over the same period. That gap is the bottleneck buyers are now paying for in stalled GPU utilisation.
SK hynix AI Infra Team Lead Seunghoon Hong and UVA's Kyusang Lee, the paper's corresponding authors, frame co-packaged optics (CPO) and optical compute interconnects as the next stage after copper traces hit a physical wall of attenuation, insertion loss and the power cost of equalisation and retiming circuitry at high data rates.
The Numbers Behind the CPO Roadmap
The paper sets out concrete targets rather than vague ambition. CPO nodes are expected to reach bandwidth density above 100Tb/s, energy efficiency under 1pJ/bit, and chip-to-chip latency under 10ns. The integration pathway runs from today's 2.5D silicon interposers toward full 3D heterogeneous stacking, with the end state extending optical links directly into the memory subsystem via a photonic interposer — enabling disaggregated, shared memory pools across an optical backplane without traditional serialisation-deserialisation penalties.
- •Node bandwidth density: greater than 100Tb/s
- •Energy efficiency: under 1pJ/bit
- •Chip-to-chip latency: under 10ns
- •Integration pathway: 2.5D interposer moving to 3D heterogeneous stacking
CPO Is Already Shipping — Just Not Everywhere Yet
This isn't purely academic. NVIDIA says its Spectrum-X Ethernet Photonics switch line, its CPO-based platform for AI factories, has been in production since 31 May 2026, claiming 5x better power efficiency, 5x longer AI uptime and 1.3x faster deployment versus transceiver-based fabrics. NVIDIA's current networking materials position broader availability in the second half of 2026, targeted at million-GPU clusters, while Quantum-X InfiniBand, initially targeted for late 2025, saw production deployments from early 2026. Buyers reviewing 800G AI back-end fabric options should treat these dates as the clearest vendor signal available for refresh planning.
Port and bandwidth specifics matter for sizing: the Spectrum-X Photonics line offers 128 ports at 800Gb/s for 102.4Tb/s total switch bandwidth, with a larger SN6800 variant reaching 512 ports at 800Gb/s for 409.6Tb/s. Cisco separately argues CPO can cut power consumption 30–40% at equivalent speeds and flatten fabric design — in some cases connecting up to 512 GPUs in a single layer and reducing larger networks from three layers to two, which directly changes switch count and latency budgets.

When to Write CPO Into an RFP — and When to Hedge
Tom's Hardware reporting frames the industry consensus clearly: CPO is moving from research to productisation, but manufacturing readiness — not the architecture itself — is the gating factor. That's why near-packaged optics is gaining traction as a hedge, with XPO modules expected in volume production during 2027 and over 100 companies having joined the XPO multi-source agreement. For a UK buyer, that means the 2026–2027 window is transitional: pluggables, near-packaged optics and true CPO will coexist, and locking a fabric contract entirely around one architecture carries risk.
There is now standards cover to lean on. The Optical Compute Interconnect MSA, formed in 2026 by AMD, Broadcom, Meta, Microsoft, NVIDIA and OpenAI, defines Gen1 at four wavelengths of 50Gb/s per channel (200Gb/s per fibre per direction), with a roadmap to 1.6Tb/s per fibre per direction. Referencing OCI MSA compliance in procurement language gives buyers a vendor-neutral anchor rather than betting on a single supplier's roadmap — something worth raising directly with an IT procurement services partner before signing multi-year fabric commitments.
Cost, Density and Design Trade-offs UK Buyers Should Model
IBM Research puts a number on the density upside: CPO can increase beachfront density by six times, which matters directly for rack-level power and space budgets in UK data halls. Combined with Cisco's flatter, fewer-layer fabric designs, the capex case shifts — fewer switch layers means fewer switches, transceivers and cabling runs to procure and maintain, though it also concentrates risk into fewer, more specialised optical components.
The clearest early proof point for accelerator-to-accelerator interconnect sits with Ayar Labs and Alchip, whose joint CPO design targets over 100Tb/s of scale-up bandwidth per accelerator and more than 256 optical scale-up ports per device — moving optical connections as close to the compute core as possible to avoid the power and latency penalties of pluggable optics. Buyers evaluating NVLink vs. InfiniBand choices, or the disaggregated memory implications tied to Compute Express Link (CXL), should note that CPO's photonic-interposer endgame is designed to serve exactly this kind of shared, low-latency memory pool.
View the data behind this chart
| Copper/Electrica… | Near-Packaged… | Co-Packaged… | |
|---|---|---|---|
| Bandwidth density | Trace-loss limited | Better, pluggable | 100Tb/s+ per node |
| Energy per bit | High, needs retime | Moderate savings | <1pJ/bit target |
| Chip-to-chip latency | Added by SerDes | Lower than copper | <10ns target |
| Volume availability | Shipping now | XPO volume 2027 | Early 2026 prod |
| Fabric layers needed | 3-layer typical | 2-3 layer | 2-layer possible |
What This Means for UK Infrastructure Planning
None of this is deployment-ready as a drop-in upgrade. Integrating low-power photonics next to high-power host logic demands thermal isolation and microfluidic or direct-to-package cooling that most UK facilities aren't yet spec'd for, and the industry still lacks standardised, low-latency coherence protocols for optically coupled memory transactions. Practically, that means treating CPO as a 2026–2027 planning horizon rather than an immediate swap-in — track AI networking adoption trends alongside your own refresh cycle, budget for phased fabric upgrades rather than a single fork-lift, and keep near-packaged optics or high-quality advanced network cards as a credible fallback if CPO manufacturing yields slip. Teams starting from scratch should also read this alongside guidance on building a UK on-prem AI cluster, since fabric choice now determines memory and interconnect flexibility for years.
- 01StorageReview — SK hynix Takes Its Co-Packaged Optics Roadmap to Nature Electronics · 21 August 2026
- 02NVIDIA Newsroom — NVIDIA Spectrum-X Co-Packaged Optics Networking Switches for AI Factories · 31 May 2026
- 03NVIDIA — Networking Silicon Photonics · 20 August 2026
- 04The Next Platform — Optical Scale-Up Fabrics Are Limited By Manufacturing, Not Architecture · 30 June 2026
- 05DataCenterDynamics — Ayar Labs, Alchip provide additional details about jointly developed CPO solution · 16 June 2026
- 06Tom's Hardware — CPO foundry roadmaps: TSMC, Intel, Samsung, GlobalFoundries · 1 July 2026
- 07Tom's Hardware — Near-packaged optics gains ground as industry hedges against CPO growing pains · 10 August 2026
- 08Cisco Blogs — Rebuilding the foundation: why AI infrastructure needs to change · 1 April 2026
- 09IBM Research — Co-packaged optics to supercharge generative AI computing · 1 February 2026
