CUDA Cores vs Tensor Cores Explained (2026 Guide)

CUDA Cores vs Tensor Cores: Two Different Answers to Two Different Questions

CUDA cores are the general-purpose parallel arithmetic units present on every Nvidia GPU since the architecture's inception. They execute one operation per thread, across thousands of threads at once, and have historically been the headline spec printed on a gaming or workstation box.

Tensor Cores are a separate hardware block, first introduced with the Volta architecture, purpose-built to perform the matrix multiply-accumulate operations that dominate neural network training and inference. Nvidia's own Tensor Cores documentation is explicit that the two blocks support different precision sets, which is the practical reason they can't be swapped for one another when reading a spec sheet: CUDA cores are listed as supporting FP64, FP32, INT32, FP16 and BF16, while current Blackwell-era Tensor Cores are listed as supporting NVFP4, FP64, TF32, BF16, FP16, FP8/FP6 and INT8.

What Are CUDA Cores? The General-Purpose Workhorses

CUDA cores behave like scalar arithmetic units operating in a single-instruction, multiple-thread pattern: every core runs the same instruction on its own slice of data, in lockstep with thousands of neighbouring cores. This is what makes them suited to rasterisation, physics, general compute and the control-flow logic that sits around any GPU workload.

Because CUDA cores carry the FP64, FP32, INT32, FP16 and BF16 precisions, they remain the part of the chip responsible for double-precision scientific work and ordinary integer or branching logic, even on a GPU purchased primarily to run AI workloads.

What Are Tensor Cores? From Volta's 640 Cores to Blackwell's Petaflops

Nvidia's Volta architecture whitepaper states the Tesla V100 contains 640 Tensor Cores, eight per streaming multiprocessor, with each Tensor Core performing 64 floating-point fused multiply-add operations per clock — meaning the eight Tensor Cores in a single SM together deliver 1,024 individual floating-point operations per clock, a dedicated matrix-math pipeline entirely separate from that SM's CUDA cores.

Nvidia's V100 datasheet lists the resulting Tensor throughput across the family: 112 TFLOPS on the base V100, 125 TFLOPS on V100S, and 130 TFLOPS on an 80GB variant, fed by 900 GB/s of memory bandwidth on V100 and 1,134 GB/s on V100S.

Blackwell has moved the goalposts on precision, not just throughput. Nvidia's Tensor Cores documentation lists Blackwell-era Tensor Core support for NVFP4, FP64, TF32, BF16, FP16, FP8/FP6 and INT8 — several formats that simply didn't exist on Volta. On raw per-GPU throughput, Nvidia's Blackwell datasheet, as republished by UK reseller OCF, lists the highest configuration at 20 PFLOPS FP4 dense and 20 PFLOPS FP4 sparse, 10 PFLOPS FP8/FP6, 5 PFLOPS FP16/BF16, and 2.5 PFLOPS TF32 for an individual Blackwell GPU. Separately, Nvidia's Blackwell architecture technical brief lists a Blackwell-class part at 15/20 petaFLOPS FP4 dense/sparse, 5/10 petaFLOPS FP8/FP6 dense/sparse, and 157.5/315 teraOPS INT8 dense/sparse — the two documents describe different configurations of the family, so treat them as distinct, separately sourced data points rather than the same chip. Anyone comparing generations should first compare NVIDIA H100, H200, and B100/B200 GPUs against the exact SKU on a quote.

Nvidia also confirms that Blackwell Ultra pulls ahead of standard Blackwell within the same family: 1.5x more AI compute FLOPS and 2x attention-layer acceleration, per Nvidia's Blackwell architecture page. "Blackwell" alone is therefore not a specific enough label on a quote — the exact SKU determines the real Tensor Core throughput.

How CUDA Cores and Tensor Cores Work Together

In a real training or inference job, CUDA cores and Tensor Cores aren't competing for the same work — they're sequential collaborators on the same die. CUDA cores handle data movement, control flow, and the scalar operations, such as activation functions, that sit either side of a matrix multiply.

Tensor Cores take over specifically for the matrix multiply-accumulate step, which dominates the FLOP count inside a transformer's attention and feed-forward layers. Nvidia's Blackwell materials show this specialisation deepening further: Blackwell Ultra's Tensor Cores add a dedicated 2x speed-up specifically for attention layers rather than a uniform lift across all compute, reflecting where modern AI workloads actually spend their arithmetic.

The same pattern reaches into workstation-class GPUs. Nvidia's RTX PRO Blackwell architecture document lists RTX Blackwell Tensor Cores as carrying FP16, BF16, TF32, INT8 and Hopper's FP8 Transformer Engine — meaning even non-data-centre GPUs increasingly share the same matrix-acceleration lineage as the racks running large-scale LLM training.

Precision Formats Explained: Why FP32, BF16, FP8 and FP4 All Exist

Precision format determines how many bits represent each number; fewer bits means more values can be multiplied per clock, at the cost of numeric range and accuracy. This is exactly why CUDA cores and Tensor Cores support different precision lists: CUDA cores carry the higher-precision, general-purpose formats — FP64, FP32, INT32, FP16, BF16 — used for scientific solvers, control logic and traditional graphics. Tensor Cores add ultra-low-precision matrix formats such as NVFP4 and FP8/FP6, alongside FP64, TF32, BF16 and FP16, because deep-learning matrix multiplies tolerate reduced precision far better than a differential equation solver does.

The scaling is visible directly in Nvidia's own Blackwell figures. On one individual Blackwell GPU, in the highest published configuration, FP4 Tensor throughput is rated at 20 PFLOPS, FP8/FP6 at 10 PFLOPS, FP16/BF16 at 5 PFLOPS, and TF32 at 2.5 PFLOPS — throughput roughly doubling each time the format's precision halves toward FP4, which is exactly why FP4 and FP8 have become the default precisions for LLM inference while FP16, BF16 and TF32 remain the standard for training.

Reading a UK Server Quote: Per-GPU vs Per-System, Dense vs Sparse

This is where CUDA-core counts actively mislead buyers. Nvidia's own Volta-to-Blackwell materials confirm that Tensor throughput is reported in precision-specific TFLOPS or PFLOPS figures, while CUDA-core count is a separate architectural metric that does not state matrix-multiply speed at all. A quote listing thousands of CUDA cores tells a UK buyer nothing about how fast that same box will train or serve a transformer model.

Scale matters just as much as precision. A single Blackwell GPU tops out around 20 PFLOPS of FP4 Tensor performance in Nvidia's highest published configuration, but Nvidia's GB200 NVL72 rack-scale platform is specified at 1,440 PFLOPS of NVFP4 Tensor performance and 720 PFLOPS of FP8/FP6 performance across the whole system — alongside 31 TB of total fast memory, 576 TB/s of aggregate memory bandwidth (worth understanding via our guide to High Bandwidth Memory (HBM)) and 130 TB/s of total NVLink bandwidth, which is best read alongside a primer on how to understand GPU interconnects like NVLink and Infiniband.

Before comparing pound-denominated quotes across OEMs and integrators, UK buyers should get three things confirmed in writing: whether the quoted PFLOPS or TFLOPS figure is per GPU or per system; whether it's dense or sparse mode (sparse figures can effectively double the dense number for the same precision); and which precision is being quoted, since FP4 and FP8 numbers will always look larger than FP16 or TF32 numbers taken from the same hardware. Normalising these three variables before comparing offers — or running the workload through a sizing tool to calculate your AI GPU requirements — is the difference between comparing like-for-like hardware and comparing marketing headlines.

Workload Suitability: Which Core Type Actually Wins

Not every workload benefits from Tensor Cores, and not every Tensor-Core-rich GPU is wasted on non-AI work. Traditional rasterised graphics and general-purpose scientific simulation still run primarily through CUDA cores, using the FP32 and FP64 precisions those cores are built for. LLM training and inference, by contrast, are dominated by matrix multiplies and lean on Tensor Cores running BF16/TF32 for training and FP8/FP4 for inference.

Data preprocessing, orchestration and anything involving branching logic or integer work still routes through CUDA cores regardless of how AI-focused the GPU is marketed to be — which is also why a card can be simultaneously excellent for AI inference and perfectly usable for general compute tasks in the same pipeline.

Programming Model and What Comes After Blackwell

Developers rarely address Tensor Cores directly. CUDA is Nvidia's general programming layer; on top of it, libraries such as cuDNN and TensorRT detect matrix-multiply operations inside a model graph and route them to Tensor Cores automatically, selecting an appropriate precision without the developer writing Tensor Core instructions by hand. This abstraction is why a model can move from a Volta-era V100 to a Blackwell GPU and automatically use whichever Tensor Core precisions the newer hardware exposes, without the matrix-multiply code itself being rewritten.

On direction of travel, Nvidia's own Blackwell Ultra numbers show where the next round of specialisation is landing: 1.5x more AI compute FLOPS and a targeted 2x speed-up specifically for attention layers, rather than a uniform lift across every operation. That pattern — adding new low-precision formats and dedicating extra Tensor Core throughput to whichever arithmetic pattern dominates current model architectures — is the clearest signal in Nvidia's published materials for how post-Blackwell Tensor Cores are likely to keep evolving: not by growing CUDA-core counts, but by adding narrower, faster matrix paths for the operations that matter most in the next generation of models. Teams sizing a deployment against these trends can start from a proper server configuration rather than a CUDA-core headline.

Sources

Every figure in this article traces to the sources below.

• •NVIDIA — Tesla V100 datasheet: Tensor Core count and per-variant TFLOPS figures
• •NVIDIA — Volta architecture whitepaper: Tensor Core design and per-clock FLOP counts
• •NVIDIA — Tensor Cores page: precision support for CUDA cores vs Tensor Cores
• •NVIDIA — Blackwell architecture page: Blackwell Ultra AI compute and attention-layer uplift
• •OCF — Blackwell datasheet: per-GPU and GB200 NVL72 system-level Tensor throughput
• •device.report — Blackwell architecture technical brief: dense/sparse Tensor throughput by precision
• •NVIDIA — RTX PRO Blackwell GPU architecture document: workstation Tensor Core precision support