32 × 100G QSFP28
32 × 100G ports with breakout support (4 × 25G per port) — providing the highest density campus core switching with full non-blocking performance.
32 × 100G Campus Core — 6.4 Tbps Non-Blocking Performance
The Cisco Catalyst 9500-32C delivers 32 × 100G QSFP28 ports with 6.4 Tbps non-blocking switching — the definitive campus core and high-performance aggregation switch for large enterprise networks.
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32 × 100G ports with breakout support (4 × 25G per port) — providing the highest density campus core switching with full non-blocking performance.
6.4 Tbps of non-blocking Layer 2/3 switching capacity — ensuring zero packet loss even at maximum 100G interface utilisation on all 32 ports simultaneously.
Two C9500-32C switches combine into a single logical chassis with StackWise Virtual — providing dual-core redundancy and cross-switch EtherChannel.
Deployed as the SD-Access campus core or border node in DNA Center fabric — connecting multiple distribution nodes and data centre networks over 100G.
Hardware MACsec encryption on all 32 × 100G ports — securing all inter-switch links in the campus core without performance penalty.
Cisco's third-generation Unified Access Data Plane ASIC — programmable, future-proof, and capable of new forwarding features via software updates.
In-Service Software Upgrades allow Cisco IOS-XE to be updated on an active switch without traffic disruption — essential for 24/7 campus core operation.
The Cisco Catalyst 9500-32C is the flagship fixed-configuration campus core switch in the Catalyst 9500 family — delivering 32 × 100G QSFP28 ports with 6.4 Tbps of non-blocking Layer 2/3 switching capacity. It is designed for large enterprise campus cores, high-performance aggregation tiers, and SD-Access border deployments requiring 100G density.
Each of the 32 × 100G QSFP28 ports supports cable breakout, allowing a single 100G QSFP28 to be broken into 4 × 25G SFP28 connections — significantly increasing effective port density for connecting 25G access switches or servers. StackWise Virtual pairs two C9500-32C switches into a single logical chassis, providing dual-core high availability and cross-switch EtherChannel for loop-free designs without spanning tree.
The C9500-32C runs Cisco IOS-XE with full model-driven programmability (YANG/NETCONF/RESTCONF/gRPC) and integrates natively with Cisco DNA Center — serving as the SD-Access campus core, transit, or border node. In this role, it routes between campus fabric VNIs, connects to data centre switching fabrics, and handles WAN edge connectivity — all with automated policy from DNA Center.
Hardware MACsec IEEE 802.1AE on all 32 × 100G ports secures every inter-switch link in the campus core without throughput degradation — ensuring encrypted data flows between aggregation and core layers even in shared or co-location environments. The Cisco Uadp 3.0 ASIC provides the programmable data plane foundation for future feature delivery without hardware replacement.
32 × 100G provides a high-performance non-blocking campus core for large enterprise networks with multiple 9400/9500-48Y4C distribution switches.
DNA Center SD-Access border node — connecting campus fabric to data centre and WAN at 100G speeds.
StackWise Virtual pairs two C9500-32C switches for high-availability dual-core design with cross-switch port channels.
Modern replacement for Catalyst 6500/6807 campus core with 100G density, programmable ASIC, and DNA Center.
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